1. Field of the Invention
The present invention relates to a semiconductor memory device and a data storage method. In particular, the present invention relates to a semiconductor memory device including a cell array having memory cells arranged in a lattice pattern, and a data storage method for a semiconductor memory device.
2. Description of Related Art
In recent years, with the advancement of information processing technologies, there is a demand for an increase in data processing speed. In information processing such as a matrix calculation or image processing, data defining a multidimensional space is handled in some cases. For example, in the image processing, along with the achievement of higher definition of a display device, there is a demand for displaying more pixels at higher speed. In view of this, there is proposed a technique in which, by using a memory device having memory cells arranged in a lattice pattern, a multidimensional space is reproduced in the memory device and an address in the space of data is associated with an address in the memory device, to thereby increase the data processing speed. Examples of such a data processing method are disclosed in Japanese Unexamined Patent Application Publication No. 05-120121, Japanese Unexamined Patent Application Publication No. 09-259035, Japanese Unexamined Patent Application Publication No. 10-112179, and Japanese Unexamined Patent Application Publication No. 05-257458.
FIG. 41 shows a block diagram of a semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. 05-120121. In this example, image data is stored in an information storage unit having memory cells two-dimensionally arranged. Further, a temporary row/column number generation unit 102, a column corresponding conversion unit 103, and a row corresponding conversion unit 104 are used to replace a row number and a column number for specifying memory cells. Thus, with the technology disclosed in Japanese Unexamined Patent Application Publication No. 05-120121, row/column replacement processing for image data can be carried out at high speed.
FIG. 42 shows a block diagram of a semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. 09-259035. In this example, a two-dimensional image is temporarily written into a memory cell array 210 before a combination of a row address and a column address is changed by using selection circuits M1 and M2, whereby rotation transformation processing or linear symmetric transformation processing for an image is performed. Thus, with the technology disclosed in Japanese Unexamined Patent Application Publication No. 09-259035, the rotation transformation processing or the linear symmetric transformation processing for an image can be carried out at high speed.
FIG. 43 shows a block diagram of a semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. 10-112179. In this example, the semiconductor memory device includes a plurality of sub-arrays 306-0 to 306-7. Pieces of data in different rows among pieces of rectangle data are stored in different sub-arrays. Then, writing and reading of data are performed in parallel, whereby the increase in processing speed is achieved.
FIG. 44 shows a block diagram of a semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. 05-257458. In this example, the semiconductor memory device includes an address conversion unit 402 for converting a logical address of each pixel forming an image, into a physical address indicating a location of a cell in a memory. Further, the address conversion unit 402 generates the physical address so that pixel data is arranged in the memory with high efficiency. Thus, with the technology disclosed in Japanese Unexamined Patent Application Publication No. 05-257458, an efficient use of a memory is achieved.
However, in the technologies disclosed in Japanese Unexamined Patent Application Publication No. 05-120121, Japanese Unexamined Patent Application Publication No. 09-259035, Japanese Unexamined Patent Application Publication No. 10-112179, and Japanese Unexamined Patent Application Publication No. 05-257458, image data is divided into cells, which are connected to different word lines, to be stored. When a dynamic random access memory (DRAM) is used as a memory device, in the memory, cells arranged in a row direction are selected by selecting any of the word lines, and cells arranged in a column direction are selected by selecting any of sense amplifiers. Accordingly, in the related arts, it is necessary to drive a plurality of word lines during a writing operation or a reading operation for image data. In view of the foregoing, in the technologies disclosed in Japanese Unexamined Patent Application Publication No. 05-120121, Japanese Unexamined Patent Application Publication No. 09-259035, Japanese Unexamined Patent Application Publication No. 10-112179, and Japanese Unexamined Patent Application Publication No. 05-257458, there arises a problem in that a power consumption increases according to the number of word lines to be driven. In the field of a semiconductor device mounted to a portable device or the like, there is a strong demand for a reduction in power consumption. Therefore, the increase in power consumption is a serious problem.